Objective
I aspire to contribute over a decade of engineering
experience, from logic design to operating system and application
programming, to a technical lead position. I offer a solid
background in validation and understand the value of clean, clear
design practices. While I enjoy designing, I strive to ensure open
and effective communication with designers and testers to
successfully execute a design.
Work Experience:
Validation Engineer: Qualcomm,
Inc., Raleigh, NC, June 2009 - Present (contractor)
Assist with the development
of testplans for a multi-processor aware L2 cache.
Implement L2 cache testing
using a combination of Verilog, System Verilog, Perl, and a
custom CPU modelling language.
ASIC Engineer: Optimal
Technologies, (US) Inc., Raleigh, NC, May 2008 - January 2009
Determine requirements for
custom Systems on a Chip (SoCs), including a set top box on a
chip with extremely tight power requirements.
Develop simple SoC modules and
codecs that are free of patent conflicts.
Evaluate vendor Intellectual
Property through discussions with vendors and review of
specifications.
Coordinate system build and synthesis.
Staff Engineer: IBM,
RTP, NC, June 1995 - May 2008
1995: PowerPC 403GCX,
401
Operated Quickturn FPGA-based logic emulation hardware.
Developed interface boards and test submission/control systems.
Automated large portions of the job with Perl and Ksh scripts.
1997: PowerPC 405, Set-Top Box
reference platform
Developed validation plans for unit-based
module testing with implementation done using C++ coordinated
with Verilog simulation.
1999: PowerPC 440
Worked
with Aptix FAEs to develop a system capable of running Linux
using their FPGA-based logic emulation hardware.
2001: PowerPC 460
Co-developed
new front-end validation methodology and testplans. Rewrote
Perl/CGI wed-based test results reporting using PHP/MySQL to
improve test and test reporting throughput. Oversaw two interns
developing validation code coverage tools.
2003: PowerPC 450
Maintained
instruction cache unit through a remap of PowerPC 440 to 90nm
technology. Improved unit timing with a variety of RTL and
physical design changes while maintaining the unit verification
2005: PowerPC 464
Made
architectural changes to improve the speed and worked with
physical design engineers to make major structural improvements.
Continued to maintain validation tests.
2008:
Engineered major architectural modifications for
latest processor (some redesign/some remap). Providing
supervision as instruction cache unit lead.
Software Engineer: Data
General, RTP, NC, May 1993 - June 1995
Developed tests for new
functionality in DG/UX (Data General's UNIX)
Developed automation tools for
test engineers
Executed tests on DG/UX and interpreting results
Teaching/Research Assistant: NCSU,
1990-1995
Electrical Engineering
Department: Assisted students with major hardware and software
projects
Computer Science Department:
UNIX system programmer/administrator
Textile Engineering Department:
UNIX system software development
Mechanical Engineering Department: Hardware developer for
Mars Mission Research Project
- Computer Languages:
-
Assembly(PowerPC/6502/6800/8051/68000), C, Perl, C++, MySQL, PHP,
Verilog, VHDL, Tcl/Tk, EDIF, Shell(tcsh/ksh/and others), Motif/X,
Lisp, HTML, Python
-
Operating Systems:
-
UNIX (Most variations, esp. Linux), Macintosh, MS-DOS, Windows
(various flavors), Amiga-DOS
-
Education:
-
MS Computer Engineering, NC State
University, May 1996 (GPA: 3.5)
BS Electrical Engineering,
NCSU, May 1993 (GPA: 3.33)
BS
Computer Engineering, NCSU,
May 1993 (GPA: 3.33)
High School Diploma, NC
School of Science and Math, June 1988
-
Activities and Organizations:
-
Amateur auto mechanic, recreational programmer and electronics
hobbyist, avid reader and film fan, live music aficionado,
occasional gardener and cook.
References Available Upon Request.
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