307 Meredith Street
Raleigh, NC 27606


I aspire to contribute over two decades of engineering experience - from logic validation to operating system and application programming - to a technical lead position. I offer a solid background in logic validation and understand the value of clean, clear design practices. I strive to ensure open, effective communication with designers and testers to successfully execute a design.

Work Experience:

Senior Verification Engineer: Nvidia, Inc., Durham, NC, August 2018 - present

Senior Staff Verification Engineer: Qualcomm, Inc., Raleigh, NC, June 2009 - July 2018

  • 2012: Unit Verification Lead, Execution Unit, Snapdragon Kryo and Centriq cores.
    Key developer and manager of the design and implementation of a System Verliog/UVM based unit test environment. Coordinated coverage generation and evaluation; feeding back into design stimulus.

  • 2011: Unit Validation Lead, Floating Point Unit, Snapdragon Krait core
    Maintained/Improved validation environment. Developed new tests and closed coverage.

  • 2010: Random Testcase Generator
    Contributed to the development of a random assembly-language test generator (written in C++). Improved a documentation web application.

  • 2009: L2 Processor Cache, Snapdragon Scorpion core
    Assisted with testplan development, and implemented testing testing using a combination of Verilog, System Verilog, Perl, and a custom CPU modeling language.

ASIC Engineer: Optimal Technologies, (US) Inc. Raleigh, NC, May 2008 - January 2009

  • Determined requirements for custom Systems on a Chip (SoCs), including a set top box on a chip with extremely tight power requirements.

  • Developed simple SoC modules and codecs that are free of patent conflicts.

  • Evaluated vendor Intellectual Property through discussions with vendors and review of specifications.

Staff Engineer: IBM, RTP, NC, June 1995 - May 2008

  • 2008:
    Engineered major architectural modifications for latest processor (some redesign/some remap). Providing supervision as instruction cache unit lead.

  • 2005: PowerPC 464
    Made architectural changes to improve the speed and worked with physical design engineers to make major structural improvements. Continued to maintain validation tests.

  • 2003: PowerPC 450
    Maintained instruction cache unit through a remap of PowerPC 440 to 90nm technology. Improved unit timing with a variety of RTL and physical design changes while maintaining the unit verification

  • 2001: PowerPC 460
    Co-developed new front-end validation methodology and testplans. Rewrote Perl/CGI web-based test results reporting using PHP/MySQL to improve test and test reporting throughput. Oversaw two interns developing validation code coverage tools.

  • 1999: PowerPC 440
    Worked with Aptix FAEs to develop a system capable of running Linux using their FPGA-based logic emulation hardware.

  • 1997: PowerPC 405, Set-Top Box reference platform
    Developed validation plans for unit-based module testing with implementation done using C++ coordinated with Verilog simulation.

  • 1995: PowerPC 403GCX, 401
    Operated Quickturn FPGA-based logic emulation hardware. Developed interface boards and test submission/control systems. Automated large portions of the job with Perl and Ksh scripts.

Software Engineer: Data General, RTP, NC, May 1993 - June 1995

  • Developed tests for new functionality in DG/UX (Data General's UNIX)

  • Developed automation tools for test engineers

  • Executed tests on DG/UX and interpreting results

Teaching/Research Assistant: NCSU, 1990-1995

Computer Languages:
Assembly(ARM,PowerPC/6502/6800/8051/68000), Verilog, System Verilog, C, Perl, C++, UVM, MySQL, JavaScript, PHP, VHDL, Tcl/Tk, EDIF, Shell(bash/tcsh/and others), Motif/X, Lisp, HTML, Python
Operating Systems:
UNIX (Most variations, esp. Linux), Macintosh, MS-DOS, Windows
MS Computer Engineering, NC State University, May 1996 (GPA: 3.5)
BS Electrical Engineering, NCSU, May 1993 (GPA: 3.33)
BS Computer Engineering, NCSU, May 1993 (GPA: 3.33)
High School Diploma, NC School of Science and Math, June 1988
Activities and Organizations:
Recreational programmer and electronics hobbyist, avid reader and film fan, live music aficionado, occasional gardener and cook.

References Available Upon Request.